library IEEE;
    use IEEE.std_logic_1164.all;
    use IEEE.numeric_bit.all;

entity ADDR is
    port(ADDR1MUX_out,ADDR2MUX_out: in unsigned(15 downto 0);
         ADDR_out: out unsigned(15 downto 0));
    end entity ADDR;
     
architecture build of ADDR is
    begin
        process(ADDR1MUX_out,ADDR2MUX_out)
            begin
                ADDR_out <= ADDR1MUX_out + ADDR2MUX_out;
            end process;
    end build;
